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 Shuai Wang
Associate Professor |
406 Department of Computer Science and
Technology Building Nanjing University, Xian Lin Campus 163 Xian Lin Da Dao, Nanjing, Jiang Su, China 210046 Email: swang at nju dot edu dot cn Web: http://cs.nju.edu.cn/swang |
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Recent News:
Prof. Wang serves as the associate editor of Journal of Circuits, Systems and Computers (JCSC)
Short Bio:
Shuai Wang received his B.S. degree in Computer Science from Nanjing University in 2003, and his Ph.D. degree in Computer Engineering from New Jersey Institute of Technology in 2010. He joined the Department of Computer Science and Technology at Nanjing University in 2011.
Research Interests:
Computer Architecture, Reliable Microarchitectures, Power/Thermal-Aware Systems, Embedded Systems, High-Performance Parallel Computing, and On-Chip Networks.
Publications:
Journals:
Shuai Wang, Guangshan Duan, Yupeng Li, and Qianhao Dong. Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime. To appear in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017.
Shuai Wang, Tao Jin, Chuanlei Zheng, and Guangshan Duan. Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing. Journal of Circuits, Systems, and Computers (JCSC), Volume 25, Issue 9, 2016. (PDF)
Shuai Wang and Guangshan Duan. On the Characterization and Optimization of System-Level Vulnerability for Instruction Caches in Embedded Processors. Microprocessors and Microsystems, Volume 38, Issue 8, pp 686 - 692, November 2015. (PDF)
Shuai Wang and Tao Jin. Wireless Network-on-Chip: A Survey. IET Journal of Engineering (IET JOE), April, 2014. (PDF)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 20, Issue 4, pp. 643 - 654, April 2012. (PDF)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. Exploring BTB Access Filtering for Low-Energy and High-Performance Microarchitectures. IET Computers & Digital Techniques (IET CDT), Volume 6, Issue 1, pp. 50 - 58, January 2012. (PDF)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Transactions on Computers (TC), Volume 58, Issue 9, pp. 1171 - 1184, September 2009. (PDF)
Jie Hu, Shuai Wang, and Sotirios G. Ziavras. On the Exploitation of Narrow-Width Values for Improving Register File Reliability. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 17, Issue 7, pp. 953 - 963. July 2009. (PDF)
Jie Hu, Johnsy K. John, and Shuai Wang. Thermal-Aware Subarrayed Data Cache Microarchitectures. International Journal of Intelligent Control and Systems (IJICS), Volume 13, No. 4, pp. 251 - 263, December 2008. (PDF)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 27, Issue 8, pp. 1503 - 1507, August 2008. (PDF)
Shuai Wang, Hongyan Yang, Jie Hu, and Sotirios G. Ziavras. Asymmetrically Banked Value-Aware Register Files for Low Energy and High Performance. Microprocessors and Microsystems, Volume 32, Issue 3, pp. 171 - 182, May 2008. (PDF)
Conferences:
Chuanlei Zheng and Shuai Wang. Characterizing Soft Error Vulnerability of Cache Coherence Protocols for Chip-Multiprocessors. In Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2014), pp. 15 - 20, Amsterdam, Netherlands, Oct. 1-3, 2014. (PDF)
Guangshan Duan and Shuai Wang. Exploiting Narrow-Width Values for Improving Non-Volatile Cache Lifetime. In Proc. of the Conference on Design, Automation and Test in Europe (DATE 2014), Dresden, Germany, March 24-28, 2014. (accepted 313 out of 1090 submissions, acceptance rate: 29%) (PDF)
Tao Jin and Shuai Wang. 1-to-Many and Many-to-1 Communication in Hybrid Wireless Network-on-Chip. In Proc. of the IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2013), pp. 497 - 500, Abu Dhabi, UAE, December 8-11, 2013. (PDF)
Shuai Wang, Guangshan Duan, Chuanlei Zheng, and Tao Jin. Combating NBTI-Induced Aging in Data Caches. In Proc. of the ACM Great Lakes Symposium on VLSI (GLSVLSI 2013), pp. 215 - 220, Paris, France, May 2-3, 2013. (accepted 51 out of 238 submissions, acceptance rate: 21%) (PDF)
Chuanlei Zheng, Parijat Shukla, Shuai Wang, and Jie Hu. Exploring Hardware Transaction Processing for Reliable Computing in Chip-Multiprocessors against Soft Errors. In Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), pp. 92 - 97, Austin, Texas, Oct. 3-5, 2012. (PDF)
Tao Jin and Shuai Wang. Aging-Aware Instruction Cache Design by Duty Cycle Balancing. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2012), pp. 195 - 200, Amherst, MA, August 19-21, 2012. (accepted 66 out of 292 submissions, acceptance rate: 23%) (PDF)
Shuai Wang, Tao Jin, Chuanlei Zheng, and Guangshan Duan. Low Power Aging-Aware Register File Design by Duty Cycle Balancing. In Proc. of the Conference on Design, Automation and Test in Europe (DATE 2012), pp. 546 - 549, Dresden, Germany, March 12-16, 2012. (accepted 279 out of 974 submissions, acceptance rate: 29%) (PDF)
Shuai Wang. Characterizing System-Level Vulnerability for Instruction Caches against Soft Errors. In Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011), pp. 356 - 363, Vancouver, Canada, October 3-5, 2011. (PDF)
Li Tang, Shuai Wang, Jie Hu, and Xiaobo Sharon Hu. Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011), pp. 266 - 271, Chennai, India, July 4-6, 2011. (accepted 52 out of 248 submissions, acceptance rate: 21%) (PDF)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), pp. 310 - 315, Lixouri Kefalonia, Greece, July 5-7, 2010. (accepted 77 out of 240 submissions, acceptance rate: 32%) (PDF)
Shuai Wang, Jie Hu, Sotirios G. Ziavras, and Sung Woo Chung. Exploiting Narrow-Width Values for Thermal-Aware Register File Designs. In Proc. of the Conference on Design, Automation and Test in Europe (DATE 2009), pp. 1422 - 1427, Nice, France, April 20-24, 2009. (accepted 226 out of 965 submissions, acceptance rate: 23%) (PDF)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. BTB Access Filtering: A Low Energy and High Performance Design. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), pp. 81 - 86, Montpellier, France, April 7-9, 2008. (accepted 74 out of 245 submissions, acceptance rate: 30%) (Best Paper Award Nomination) (PDF)
Shuai Wang, Hongyan Yang, Jie Hu, and Sotirios G. Ziavras. Asymmetrically Banked Value-Aware Register Files. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), pp. 363 - 368, Porto Alegre, Brazil, May 9-11, 2007. (accepted 66 out of 174 submissions, acceptance rate: 38%) (PDF)
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, and Jie Hu. Vector Processing Support for FPGA-Oriented High Performance Applications. In Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), pp. 447 - 448, Porto Alegre, Brazil, May 9-11, 2007. (Poster, accepted 27 out of 174 submissions) (PDF)
Shuai Wang, Jie Hu, and Sotirios G. Ziavras. On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. In Proc. of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS VI), pp. 14 - 20, Samos, Greece, July 17-20, 2006. (accepted 26 (for IC-SAMOS) out of 130 submissions, acceptance rate: 20%) (PDF)
Jie Hu, Shuai Wang and Sotirios G. Ziavras. In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. In Proc. of the International Conference on Dependable Systems and Networks (DSN 2006) - Dependable Computing and Communications Symposium (DCCS), pp. 281 - 290, Philadelphia, PA, June 25-28, 2006. (accepted 34 out of 187 submissions, acceptance rate: 18%) (PDF)
Jie Hu, Greg M. Link, Johnsy John, Shuai Wang, Sotirios G. Ziavras. Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. In Proc. of the Asia-Pacific Computer Systems Architecture Conference (ACSAC 2005), pp. 200 - 214, Singapore, October 24-26, 2005. (accepted 65 out of 173 submissions, acceptance rate: 37%) (PDF)
Workshops:
Rong Gu, Yun Tang, Zhaokang Wang, Shuai Wang, Xusen Yin, Chunfeng Yuan, and Yihua Huang. Efficient Large Scale Distributed Matrix Computation with Spark. Workshop on Mining Big Data in Social Networks in conjunction with the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, October 29 - November 1, 2015. (PDF)
Rong Gu, Yun Tang, Qianhao Dong, Zhaokang Wang, Zhiqiang Liu, Shuai Wang, Chunfeng Yuan, Yihua Huang. Unified Programming Model and Software Framework for Big Data Machine Learning and Data Analytics. Workshop on Dependable Software and Applications in conjunction with the Annual IEEE Computer Software and Applications Conference (COMPSAC 2015), Taiwan - July 1-5, 2015. (PDF)
Guangshan Duan, Chuanlei Zheng, Tao Jin, and Shuai Wang. Combating NBTI-Induced Aging in Data Caches. Workshop on Resilient Architectures (WRA) in conjunction with the 45th Annual International Symposium on Microarchitecture (MICRO-45), Vancouver, Canada, December 2, 2012.
Shuai Wang and Tao Jin. Aging-Aware Reliable Register File Design by Duty Cycle Balancing. Workshop on Resilient Architectures (WRA) in conjunction with the 44th Annual International Symposium on Microarchitecture (MICRO-44), Porto Alegre, Brazil, December 4, 2011.
Patents:
Replicating tag entries for reliability enhancement in cache tag arrays. U.S. Patent (U.S. Patent No.US8838897).
Teaching:
Professional Activities:
Membership in Professional Associations: Institute of Electrical and Electronics Engineers (IEEE), IEEE Computer Society, Association for Computing Machinery (ACM), ACM Special Interest Group on Computer Architecture (ACM SIGARCH), IEEE Technical Committee on Computer Architecture (TCCA), IEEE Technical Committee on Dependable Computing and Fault Tolerance (TCFT), IEEE Technical Committee on Microprocessors and Microcomputers (TCMM), IEEE Technical Committee on Microprogramming and Microarchitecture (TCuARCH).
l Associate Editor: Journal of Circuits, Systems and Computers (JCSC)
l Conference Program Committee Member: IEEE International Conference on Computer Design (ICCD 2013), International Conference on Tools with Artificial Intelligence (ICTAI 2009), AICIT¡¯s International Conference.
l Journal Reviewer: IEEE Transactions on Computers (TC), IEEE Transactions on Parallel and Distributed Systems (TPDS), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE Embedded Systems Letters (ESL), IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), ACM Transactions on Autonomous and Adaptive Systems (TAAS), IET Computers & Digital Techniques (IET CDT), Journal of Systems Architecture (JSA), International Journal of Electronics, Journal of Electronic Testing: Theory and Applications (JETT), Journal of Circuits Systems and Computer (JCSC), Simulation Modelling Practice and Theory (SIMPAT), International Journal on Advances in Information Sciences and Service Sciences (AISS), Journal of Zhejiang University Science C (Computers & Electronics).
l Conference Reviewer: ICCD 2013, ASP-DAC 2013, VLSI Design 2011, IC3 2011, TechSym, 2011,NCM 2011, IDCAT 2011, ICNIT 2011, VLSI Design 2010, ICTAI 2009, IC3 2008, SAMOS 2007, CASES 2006.
Resource Links:
Upcoming Computer Architecture Conferences
Computer Architecture Research Groups
